1. Field of the Invention
The present invention relates in general to voltage detectors. In particular, the present invention relates to a source voltage detector logic circuit having smaller temperature dependency and reverse drift effects than those of conventional circuits in the critical threshold voltages of the constituting NMOS and PMOS transistors thereof for stable voltage detection operation.
2. Description of Related Art
Voltage detectors are widely utilized in digital electronic circuits. The result of voltage detection provides the basis on which to determine whether or not to initiate a particular system logic function. In a microprocessor-based computer system, for example, a source voltage detector is utilized to detect the voltage level of the power supply voltage in its memory subsystem. The voltage detector provides a signal to auxiliary circuitry that controls the power supply voltage to the memory blocks of the computer system.
The majority of the desktop personal computer systems still employ 3-volt logic circuits. Recently, however, there has been a trend, at least among microprocessors used as CPUs in desktop computers, toward the use of 3-volt logic. The purpose of the reduced voltage is to diminish thermal dissipation and save power. However, the rest of the computer system (other than the microprocessor and its associated circuitry) still requires the more popular 5-volt power supply. In the case of desktop computer systems, this is particularly true. The vast majority of peripheral devices, including those on boards that plug into computer expansion slots, operate on 5-volts.
The change to the 3-volt design is, therefore, much restricted in these desktop systems, at least when compared to the other sector of the microprocessor-based personal computer industry, that is, the portable computers, or, the notebook computers, as they are more frequently referred to.
Among the most important design considerations for portable computers is the extension of battery life. Power management techniques have been developed and are beneficial. However, further extension of battery life can be obtained simply by reducing operating voltages for the entire computer. The reduction of the power supply voltage not only reduces the power consumption rate, but also reduces the heat dissipation that, in the much confined cabinet environment such as in a notebook computer, if not carefully handled, may easily restrict the usefulness of the notebook computer.
Thus, a trend is developing in the adoption of lower voltage levels. A voltage level of 3 volts seems to be the standard to which more and more manufactures are adhering. Of course, there are many computer systems operating at 5-volts that have considerable useful life remaining. Therefore, the various computer components must remain 5-volt compatible during a transitional period from a 5-volt standard to a 3-volt standard.
In view of this, many digital components for the personal computer systems are now designed to be operated at either 5 or 3 volts. For example, SRAM devices are frequently utilized as the building blocks for secondary cache memory subsystems of modern high-speed microprocessor-based personal computer systems. They are therefore among the first components that should be adapted to operate at either 5 or 3 volts. This is because in many low-cost computer system designs, the data bus of the SRAM-based secondary cache memory subsystem is directly tied to the data bus of the CPU. There is a similar situation in DRAM devices when they are installed in these 3-volt computer systems.
For the SRAM devices to be able to adapt to both the 5- and 3-volt operating modes, a voltage detector is integrated into the SRAM memory subsystems to detect the system power supply voltage, so that the detected result can be employed as the basis for a determination concerning either the higher 5-volt or the lower 3-volt power should be supplied. With this power supply detection, as well as the adjustment capability present in the computer systems, SRAM manufacturers will not be required to make two different types of SRAM devices, one for 3- and one for 5-volt systems. However, in the conventional notebook computer system designs, the supply voltage detection circuitry, as well as the necessary power supply adjustment circuitry, both constitute a complication to the overall logic system of the entire notebook computer. The following is a brief description of those conventional circuits.
FIG. 1 (Prior Art) is a schematic diagram of the logic circuitry of a conventional voltage detector. The front-end detector 3 of the conventional voltage detector comprises a PMOS transistor MP1 connected in series with an NMOS transistor MN1. The gate and source terminals of both the PMOS transistor MP1 and the NMOS transistor MN1 are tied together and then connected together to constitute an upper load element. The output voltage at the drain of the NMOS transistor MN1, as designated by V.sub.1, may be determined by EQU V.sub.1 -V.sub.CC -.vertline.V.sub.TP1 .vertline.-.vertline.V.sub.TM1 .vertline.
wherein V.sub.TP1 and V.sub.TM1 are the threshold voltages of the transistors MP1 and MN1 respectively. Another NMOS transistor MN2 has its gate terminal tied to the series connection joint of the transistors MN1 and MP1 and its drain terminal connected to the source of the transistor MN1, while its source terminal is connected to the system ground plane. This prevents the floating of the upper load element consisting of the transistors MP1 and MN1, and allows the output voltage V.sub.1 to be pulled up substantially to the V.sub.CC potential.
The output voltage of this conventional basic front-end detector 3, namely, voltage V.sub.1, is coupled to the input of a logic inverter INV1 connected as the succeeding stage that takes up V.sub.1 as input as either a logical high, or a logical low signal. The logical high/low status of this voltage V.sub.1 is generally determined by parameters including the power supply voltage V.sub.CC, as well as the width/length ratio (W/L ratio) of the channel regions of the NMOS and PMOS transistors that constitute the inverter INV1. A further inverter stage INV2 may be coupled to the output of inverter INV1, the output of inverter INV2 being designated as V.sub.5.
FIG. 2 (Prior Art) is a schematic diagram of logic inverter INV1 utilized in the conventional voltage detector shown in FIG. 1 (Prior Art). The conventional CMOS inverter comprises a pair of PMOS and NMOS transistors MP2 and MN3 respectively. When the power supply voltage V.sub.CC is smaller than 3.3 V, V.sub.1 may be smaller than 1 volt. In this case, if the input transition point for this CMOS inverter INV1 is at 1/3 V.sub.CC, then V.sub.1 would be regarded as the logical low signal. On the other hand, when the power supply voltage V.sub.CC is higher than 4.5 V, the input signal V.sub.1 to this inverter would be higher than 1.9 V, which would be larger than 1/3 V.sub.CC, and would therefore be regarded as a logical high signal.
Thus, with the variation in the power supply voltage, the inverter INV1 would be able to interpret the input signal V.sub.1 to its input as either a logical low or high input signal, depending on the range of the power supply voltage V.sub.CC in the range covering 3.3 to 4.5 V. The CMOS inverter INV1 would therefore be able to output a logical high or low signal accordingly, which can be utilized as the trigger signal for an auxiliary circuitry that can actually control the power supply circuitry to provide the power source at the appropriate voltage.
However, due to the inherent nature of the semiconductor devices that are subject to the changes of controlling conditions during fabrication, electronic characteristics of the semiconductor integrated circuits drift with respect to the intended nominal value. In other words, the threshold voltages V.sub.TP and V.sub.TN for PMOS and NMOS transistors respectively would either be relatively higher and lower, or be relatively lower and higher respectively, depending on the conditions of device fabrication involved. The result is the drift of the output voltage of the inverter INV1. On the other hand, the ambient temperature conditions will also affect the threshold voltages of the PMOS and NMOS transistor devices. Normally, the higher the ambient temperature, the lower the threshold voltages V.sub.TP and V.sub.TN become. This also changes the logical transition point of the inverter, resulting in a larger range of the logical transition point for the inverter. This point is illustrated by two graphs.
FIG. 3a (Prior Art) is a characteristics curve showing the output voltage V.sub.3 of inverter INV1 versus the power supply voltage V.sub.CC of the conventional voltage detector arrangement shown in FIG. 1 (Prior Art). The three different characteristic curves depicted in the drawing represent three possibly different curves depending on the conditions that existed during device fabrication and on device operating temperature. There are, of course many other possible characteristic curves. Only three are shown for simplicity. The alternative characteristic curves are schematically indicated by the left and right phantom lines.
FIG. 3b (Prior Art) is a characteristic curve showing the relationship of output voltage V.sub.5 of inverter INV2 shown in FIG. 1 (Prior Art). The direct result of this phenomena of drifting logical transition point of a conventional CMO3 inverter, such as inverter INV1 depicted in FIG. 2 (Prior Art), is the corresponding drifting of the output voltage V.sub.5 of inverter INV2. This drifting manifests itself as a drifting of the power supply voltage transition value V.sub.TR, as outlined by the left and right phantom lines in FIG. 3b (Prior Art). Such characteristics drifting phenomena severely confines the useful range of operating conditions. In other words, in a system with larger characteristic drifting effect, the operating temperature range is smaller, and the system must be restricted to the operation of limited speed range.